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is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 1 features ? single power supply operation - low voltage range: 2. 3 v - 3.6 v ? memory organization - is 25 l q0 80 : 1024 k x 8 ( 8 mbit) ? cost effective sector/block architecture - 8 mb : uniform 4kbyte sectors / sixteen uniform 64kbyte blocks ? serial per ipheral interface (spi) compatible - s upports s ingle - , dual - or quad - output - supports spi modes 0 and 3 - maximum 33 mhz clock rate for normal read - maximum 1 0 4 mhz clock rate for fast read - maximum 20 8 mhz clock rate - maximum 4 00 mh z clock rate equivalent quad spi ? byte program operation - typical 10 u s/byte ? page program (up to 256 bytes) operation - maximum 0. 7 ms per pa ge program ? sector, block or chip erase operation - sector erase (4kb) ? 1 5 0ms (typ) - block erase (64kb) ? 50 0 ms (typ) - chip erase ? 2 s ( 8 mb) ? low power consumption - max 12 ma active read current - max 20 ma program/erase current - max 3 0 u a standby current ? hardware write protection - protect and unprotect the de vice from write operation by write protect (wp#) pin ? software write protection - the block protect ( bp3, bp2, bp1, bp0) bits allow partial or entire memory to be configured as read - only ? high product endurance - guaranteed 1 00,000 program/erase cycles per single sector - minimum 20 years data retention ? industrial standard pin - out and package - 8 - pin 208mil soic - 8 - pin 150mil v vsop - 8 - contact wson - pdip - l ead - free (pb - free) package ? additional 256 - byte security information one - time programmable (otp) area ? special protect function - safe guard function (appendix 1) - sector unlock function (appendix 2) general description the is 25 l q 0 80 is 8 mbit serial peripheral interface (spi) flash memories , providing single - , dual or quad - output . the devices are designed to support a 33 mhz fclock rate in normal read mode, and 1 0 4 mhz in fast read (quad output is 100mhz) , the fastest in the industry . the devices use a single low voltage power supply, ranging from 2. 3 volt to 3.6 volt, to perform read, erase a nd program operations. the devices can be programmed in standard eprom programmers. the is 25 l q 0 80 are accessed through a 4 - wire spi interface consisting of serial data input /output (sl), serial data output (so), serial clock (sck), and chip enable (ce#) p ins. the devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in one program operation. these devices are divided into uniform 4 kbyte sectors or uniform 64 kbyte blocks. the is 25 l q 0 80 are offered in 8 - pin soic 2 08 mil , 8 - pin pdip , 8 - pin v vsop and 8 - contact wson. 8 mbit single operating voltage serial flash memory with 104 mhz dual - or 100mhz quad - output spi bus interface
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 2 connection diagrams ce# ce# gnd vcc hold# (io3) sck si (io0 ) si (io0 ) sck hold# ( io3) vcc so (io1) wp# (io2) gnd 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 8 - pin soic /vvsop 8 - contact wson wp# (io2) so (io1) hold#(io3) 8 - pin pdip 5 6 7 8 1 2 3 4 vcc nc ( io 3 ) sck si ( io 0 ) so ( io 1 ) gnd wp # ( io 2 ) ce #
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 3 pin descriptions sy mbol type description ce# input chip enable: ce# low activates the devices internal circuitries for device operation. ce# high deselects the devices and switches into standby mode to reduce the power consumption. when a device is not selected, data will not be accepted via the serial input pin (sl), and the serial output pin (so) will remain in a high impedance state. sck input serial data clock si (io0) input /output serial data input /output so (io1) input/output serial data input/ output gnd ground vcc device power supply wp# (io 2 ) input /output write protect /serial data output : a hardware program/erase protection for all or part of a memory array. when the wp# pin is low, memory array write - protection depends on the setting of bp3, bp2, bp1 and b p0 bits in the status register. when the wp# is high, the status register are not write - protected. h old # (io 3 ) input/output hold: pause serial communication by the master device without resetting the serial sequence. serial data input & output (for 4xi/o read mode)
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 4 block diagram si (io0) wp# (io 2 ) hold# (io 3 ) so (io 1 )
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 5 spi modes description multiple is 25 l q 0 80 devices can be connected on the spi serial bus and controlled by a spi master, i.e. microcontroller, as shown in figure 1. the devices support either of two spi modes: mode 0 (0, 0) mode 3 (1, 1) the difference between these two modes is the clock polarity when the spi master is in stand - by mode: the serial clock remains at 0 (sck = 0) for mode 0 and the clock remains at 1 (sck = 1) for mode 3. please refer to figure 2. for both modes, the input data is latched on the rising edge o f serial clock (sck), and the output data is available from the falling edge of sck. figure 1. connection diagram among spi master and spi slaves (memory devices) figure 2. spi modes supported msb msb sck sck so si input mode mode 0 (0,0) mode 3 (1,1) spi master (i.e. microcontroller) cs3 cs2 cs1 spi memory device spi memory devic e spi memory devi ce spi interface with (0,0) or (1,1) sd i sdi sck sck sck sck so so so si si si ce# ce# ce# wp# wp# wp# hold# hold# hold# note: 1. the write protect (wp#) and hold (hold#) signals should be driven high or low as appropriate.
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 6 syste m configuration the is 25 l q 0 80 devices are designed to interface directly with the synchronous serial peripheral interface (spi) of the motorola mc68hcxx series of microcontrollers or any spi interface - equipped system controllers. the devices have two sup erset features that can be enabled through specific software instructions and the configuration register: 1. configurable sector size: the memory array of is 25 l q 0 80 is divided into uniform 4 kbyte sectors or uniform 64 kbyte blocks (a block consists of si xteen adjacent sectors). table 1 illustrates the memory map of the devices.
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 7 block/sector addresses table 1. block/sector addresses of is 25 l q 0 80 memory density block no. (64kbyte) sector no. sector size (kbytes) address range 8mbit block 0 sector 0 4 000000h - 000fffh sector 1 4 001000h - 001fffh : : : sector 15 4 00f000h - 00ffffh block 1 sector 16 4 010000h - 010fffh sector 17 4 011000h - 011fffh : : : sector 31 4 01f000h - 01ffffh : : : : block 7 sector 127 4 0 7 0000h C 0 7 ffffh block 8 sector 128 4 0 8 0000h C 0 8 ffffh : : : : : : : : block 15 sector 255 4 0 f 0000h C 0 f ffffh
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 8 registers (continued) status register refer to tables 5 and 6 for status register f ormat and status register bit definitions. the bp0, bp1, bp2, bp3 and srwd are non - volatile memory cells that can be written by a write status register (wrsr) instruction. the default value of the bp2, bp1, bp0, and srwd bits were set to 0 at factory. t he status register can be read by the read status register (rdsr). refer to table 10 for instruction set. the function of status register bits are described as follows: wip bit : the write in progress (wip) bit is read - only, and can be used to detect the progress or completion of a program or erase operation. when the wip bit is 0, the device is ready for a write status register, program or erase operation. when the wip bit is 1, the device is busy. wel bit : the write enable latch (wel) bit indicates the status of the internal write enable latch. when the wel is 0, the write enable latch is disabled, and all write operations, including write status register, write configuration register, page program, sector erase, block and chip erase operations are inhibited. when the wel bit is 1, write operations are allowed. the wel bit is set by a write enable (wren) instruction. each write register, program and erase instruction must be preceded by a wren instruction. the wel bit can be reset by a write disab le (wrdi) instruction. it will automatically be the reset after the completion of a write instruction. bp3, bp2, bp1, bp0 bits : the block protection ( bp3, bp2, bp1 and bp0) bits are used to define the portion of the memory area to be protected. refer to t ables 7, 8 and 9 for the block write protection bit settings. when a defined combination of bp3, bp2, bp1 and bp0 bits are set, the corresponding memory area is protected. any program or erase operation to that area will be inhibited. note: a chip erase (c hip_er) instruction is executed only if all the block protection bits are set as 0s. srwd bit : the status register write disable (srwd) bit s operates in conjunction with the write protection (wp#) signal to provide a hardware protection mode. when the srwd is set to 0, the status register is not write - protected. when the srwd is set to 1 and the wp# is pulled low (v il ), the bits of status register (srwd, bp3, bp2, bp1, bp0) become read - only, and a wrsr instruction will be ignored. if the srwd is se t to 1 and wp# is pulled high (v ih ), the status register can be changed by a wrsr instruction. qe bit : the quad enable (qe) is a non - volatile bit in the status register that allows quad operation . when the qe bit is set to 0 ,the pin wp# and hold# are enable. when the qe bit is set to 1 , the pin io2 and io3 are enable. table 5. status reg ister format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srwd qe bp3 bp2 bp1 bp0 wel wip d efault (flash bit) 0 0 0 0 0 0 0 0 * the default value of the bp3, bp2, bp1, bp0, and srwd bits were set to 0 at factory.
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 9 registers (continued) table 6. status register bit definition bit name definition read - /write non - volatile bit bit 0 wip write in progress bit: "0" indicates the device is ready "1" indicates a write cycle is in progress and the device is busy r no bit 1 wel write enable latch: "0 " indicates the device is not write enabled (default) "1" indicates the device is write enabled r/w no bit 2 bp0 block protection bit: (see tables 7, 8 and 9 for details) "0" indicates the specific blocks are not write - protected (default) "1" indicates th e specific blocks are write - protected r/w yes bit 3 bp1 bit 4 bp2 bit 5 bp3 bit 6 qe quad enable bit: 0 indicates the quad output function disable (default) 1 indicates the quad output function enable r/w yes bit 7 srwd status register wr ite disable: (see table 10 for details) "0" indicates the status register is not write - protected (default) "1" indicates the status register is write - protected r/w yes table 9. block write protect bits for is 25 l q0 80 protected memory area bp3 bp2 bp1 bp0 8 mbit 0 0 0 0 none 0 0 0 1 (1 blocks : 15th): 0 0 1 0 (2 blocks :14th to 15th): 0 0 1 1 (4blocks :12th to 15th): 0 1 0 0 (8 blocks :8th to15th): 0 1 0 1 all blocks (16 blocks : 0 to 15): 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 (8 blocks :0th to 7th): 1 1 0 0 (12 blocks :0th to 11th): 1 1 0 1 (14 blocks :0th to 13th): 1 1 1 0 (15 blocks :0th to 14th): 1 1 1 1 all blocks (16blocks : 0th to 15th):
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 10 registers (continued) protection mode the is 25 l q0 80 have two types of write - protection mechanisms: hardware and software. these are used to prevent irrelevant operation in a possibly noisy environment and protect the data integrity. hardware write - protection the devices provide two hardware write - protection features: a. when inputting a program, erase or write status register instruction, the number of clock pulse is checked to determine whether it is a multiple of eight before the executing. any incomplete instruction command sequence will be ignored. b. w rite inhibit is 2.0 v, all write sequence will be ignored when vcc drop to 2.0 v and lower. c . the write protection (wp#) pin provides a hardware write protection method for bp3, bp2, bp 1 , bp0 and srwd in the status register. refer to the status register d escription. software write protection the is 25 l q0 80 also provide s two software write protection features: a. before the execution of any program, erase or write status register instruction, the write enable latch (wel) bit must be enabled by executing a write enable (wren) instruction. if the wel bit is not enabled first, the program, erase or write register instruction will be ignored. b. the block protection ( bp3, bp2, bp1, bp0) bits allow part or the whole memory area to be write - protected. table 10 . hardware write protection on status register srwd wp# status register 0 low writable 1 low protected 0 high writable 1 high writable device operation the is 25 l q0 80 utilize an 8 - bit instruction register. refer to table 1 1 instruction set for details of the instructions and instruction codes. all instructions, addresses, and data are shifted in with the most significant bit (msb) first on serial data input (si). the input data on si is latched on the rising edge of serial clock (sck) after chip enable (ce#) is driven low (v il ). every instruction sequence starts with a one - byte instruction code and is followed by address bytes, data bytes, or both address bytes and data bytes, depending on the type of instruction. ce# must be driven high (v ih ) af ter the last bit of the instruction sequence has been shifted in. the timing for each instruction is illustrated in the following operational descriptions.
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 11 table 1 1 . instruction set instruction name hex code operation comman d cycle maximum f requency rdid abh read manufacturer and product id 4 byte s 1 0 4 mhz jedec id read 9fh read manufacturer and product id by jedec id command 1 byte 1 04 mhz rdmdid 90h read manufacturer and device id 4 bytes 1 04 mhz wren 06h write enable 1 byte 1 04 mhz wr di 04h write disable 1 byte 1 04 mhz rdsr 05h read status register 1 byte 1 04 mhz wrsr 01h write status register 2 byte s 1 04 mhz read 03h read data bytes from memory at normal read mode 4 byte s 33 mhz fast_read 0bh read data bytes from memory at fast re ad mode 5 byte s 1 04 mhz frdo 3bh fast read dual output 5 bytes 1 04 mhz frdio bbh fast read dual i/o 3 bytes 1 04 mhz frqo 6bh fast read quad output 5 bytes 1 0 0 mhz frqio ebh fast read quad i/o 2 bytes 1 0 0 mhz mr ffh mode reset 2 byte 1 0 4 mhz page_ prog 0 2h page program data bytes into memory 4 bytes + 256b 1 0 4 mhz sector_er d7h/ 20h sector erase 4 bytes 1 0 4 mhz block_er (64kb) d8h block erase 64k byte 4 bytes 1 0 4 mhz chip_er c7h/ 60h chip erase 1 byte 1 04 mhz quad page program 32h page program data by tes into memory with quad interface 4 bytes + 256b p rogram/ erase suspend 75h /b0h suspend during the program/erase 104mhz program/ erase resume 7ah /30h resume program/erase 104mhz p rogram information raw b1h program 256 bytes of security area 4 bytes 104 mhz read information raw 4bh r ead 256 bytes of security area 4 bytes 33 mhz hold operation hold# is used in conjunction with ce# to select the is 25 l q0 80 . when the devices are selected and a serial sequence is underway, hold# can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, hold# is brought low while the sck signal is low. to resume serial communication, hold# is brought high while the sck signal is low (sck may still toggle duri ng hold). inputs to sl will be ignored while so is in the high impedance state.
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 12 device operation (continued) rdid command (read product identification) / operation the read product identification (rdid) instruction is for reading out the old style of 8 - bit electronic signature, whose values are shown as table of id definitions. this is not same as rdid or jedec id instructio n. its not recommended to use for new design. for new design, please use rdid or jedec id instruction. the rdes instruction code is followed by three dummy bytes, each bit being latched - in on si during the rising edge of sck. then the device id is shifted out on so with the msb first, each bit been shifted out during the falling edge of sck. the rdes instruction is ended by ce# goes high. the device id outputs repeatedly if continuously send the additional clock cycles on sck while ce# is at low. table 1 2 . product identification product identification data manufacturer id first byte 9dh second byte 7fh device id: device id 1 device id 2 is 25 l q 0 80 c 1 3 h 4 4 h figure 3. read product identification sequence 0 1 8 31 38 39 46 47 54 high impedance device id 1 device id 1 device id 1 sck ce # si so instruction 9 7 1010 1011 b 3 dummy bytes
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 13 device operation (continued) jedec id read command (read product identification by jedec id) operation the jedec id read instruction allows the user to read the manufacturer and product id of de vices. refer to table 1 2 product identification for pflash manufacturer id and device id. after the jedec id read command is input, the second manufacturer id (7fh) is shifted out on so with the msb first, followed by the first manufacturer id (9dh) and th e device id ( 4 4 h, in the case of the is 25 l q 0 80 ), each bit shifted out during the falling edge of sck. if ce# stays low after the last bit of the device id is shifted out, the manufacturer id and device id will loop until ce# is pulled high. figure 4. read product identification by jedec id read sequence sck ce # si instruction 1001 1111 b 0 8 15 23 24 31 7 16 high impedance so device id 2 manufacture id 1 manufacture id 2
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 14 device operation (continued) rdmdid command (read device manufacturer and device id) operation the read product identification (rdid) instruction allows the user to read the manufacturer and product id of the devices. refer to table 1 2 product identification for pflash? manufacturer id and device id. the rdid instruction code is followed by two dummy bytes and one byte address (a7~a0), each bit being latched - in on si during the rising edge of sck. if one byte address is initially set to a0 = 0, then the first manu facturer id (9dh) is shifted out on so with the msb first, the device id 1 and the second manufacturer id (7fh), each bit been shifted out during the falling edge of sck. if one byte address is initially set to a0 = 1, then device id 1 will be read first, th en followed by the first manufacture id (9dh) and then second manufacture id (7fh). the manufacture and device id can be read continuously, alternating from one to the others. the instruction is completed by driving ce# high. figure 5 . read product id entification by rdmd id read sequence 0 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 . . . i n s t r u c t i o n = 1 0 0 1 0 0 0 0 b . . . 2 3 2 2 2 1 3 2 1 a 0 3 - b y t e a d d r e s s c e # s c k s i o s o h i g h i m p e d a n c e 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 7 6 5 4 3 2 1 0 c e # s c k s i o s o 6 5 4 3 2 1 7 0 d a t a o u t 1 d a t a o u t 2
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 15 note : (1) address a0 = 0, will output the 1st manufacture id (9dh) first - > device id 1 - > 2nd manufacture id (7fh) address a0 = 1, will output the device id 1 - > 1st manufacture id (9d) - > 2nd manufacture id (7fh) 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 s c k s i o s o 6 5 4 3 2 1 7 0 d a t a o u t 3 c e #
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 16 device operation (continued) write enable operation the write enable (wren) instruction is used to set the write enable latch (wel) bit. the wel bit of the is 25 l q016 is reset to the write C protected state after power - up. the wel bit must be write enabled before any write operation, including sector, block erase, chip erase, page program, write status register, and write configuration register operations. the wel bit will be reset to the write - protect state automatically upon completion of a write operation. the wren instruction is required before any above operation is executed. figure 6 . write enable sequence wrdi command (write disable) operation the write disable (wrdi) instruction resets the wel bit and disables all write instructions. the wrdi instruction is not required after the execution of a write instruction, since the wel bit is automatically reset. figure 7 . write disable sequence
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 17 device operation (continued ) rdsr command ( read status register) operation the read status register (rdsr) instruction provides access to the status register. during the execution of a program, erase or write status register operation, all other instructions will be ignored except the rdsr instru ction, which can be used to check the progress or completion of an operation by reading the wip bit of status register. figure 8 . read status register sequence wrsr command (write status register) operation the write status register (wrsr) instructi on allows the user to enable or disable the block protection and status register write protection features by writing 0s or 1s into the non - volatile bp3, bp2, bp1, bp0 and srwd bits. figure 9 . write status register sequence
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 18 device operation (co ntinued) read command (read data) operation the read data (read) instruction is used to read memory data of a is 25 l q0 80 under normal mode running up to 33 mhz. the read instruction code is transmitted via the sl line, followed by three address bytes (a 23 - a0) of the first memory location to be read. a total of 24 address bits are shifted in, but only a ms (most significant address) - a0 are decoded. the remaining bits (a23 C a ms ) are ignored. the first byte addressed can be at any memory location. upon completion, any data on the sl will be ignored. refer to table 1 3 for the related address key. the first byte data (d7 - d0) addressed is then shifted out on the so line, msb first. a single byte of data, or up to the whole memory array, can be read out in one read instruction. the address is automatically incremented after each byte of data is shifted out. the read operation can be terminated at any time by driving ce# high (v ih ) after the data comes out. when the highest address of the devices is reach ed, the address counter will roll over to the 000000h address, allowing the entire memory to be read in one continuous read instruction. if a read data instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is i gnored and will not have any effects on the current cycle table 1 3 . address key address is 25 l q0 80 a n ( a ms C 0) a 19 - a0 don't care bits a23 C figure 1 2 . read data sequence
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 19 device operation (continued) fast_read command (fast read data) opera tion the fast_read instruction is used to read memory data at up to a 1 0 4 m hz clock. the fast_read instruction code is followed by three address bytes (a23 - a0) and a dummy byte (8 clocks), transmitted via the si line, with each bit latched - in during t he rising edge of sck. then the first data byte addressed is shifted out on the so line, with each bit shifted out at a maximum frequency f ct , during the falling edge of sck. the first byte addressed can be at any memory location. the address is automatic ally incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single fast_read instruction. the fast_read instruction is terminated by driving ce# high (v ih ). if a fast read data instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle figure 1 3 . fast read data sequen ce sio
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 20 device operation (continued ) frdo command (fast read dual output) operation the frdo instruction is used to read memory data on two output pins each at up to a 1 0 4 mh z clock. the frdo instruction code is followed by three address bytes (a23 C a0 ) and a dummy byte (8 clocks), transmitted via the si line, with each bit latched - in during the rising edge of sck. then the first data byte addressed is shifted out on the so and sio lines, with each pair of bit s shifted out at a maximum frequency f ct , du ring the falling edge of sck. the first bit (msb) is output on so, while simultaneously the second bit is output on sio. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted o ut. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frdo instruction. frdo instruction is terminated by driving ce# high (v ih ) . if a frdo instruction is iss ued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle figure 1 4 . f ast read dual - output sequence 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 ... instruction = 0011 1011b ... 23 22 21 3 2 1 0 3 - byte address ce# sck si so high impedance 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 ce# sck io0 io1 high impedance data out 1 data out 2 high impedance
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 21 device operation (continued ) frdio c ommand (fast read dual i/o) operation the frdio instruction is similar to the frdo instruction, but allows the address bits to be input two bits at a time . this may allow for code to be executed directly from the spi in some applications. the frdio ins truction code is followed by three address bytes (a23 C a0) and a mode byte, transmitted via the io0 and io1 lines, with each pair of bits latched - in during the rising edge of sck. the address msb is input on io1, the next bit on io0, and continue s to shif t in alternating on the two lines. the mode byte contains the value ax, where x is a dont care value. then the first data byte addressed is shifted out on the io1 and io0 lines, with each pair of bit s shifted out at a maximum frequency f ct , during the falling edge of sck. the msb is output on io 1 , while simultaneously the second bit is output on io 0 . figure 15 illustrates the timing sequence. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single fr di o instruction. fr di o instruction is terminated by driving ce# high (v ih ). the device expects the next operation will be an other frdio. it remains in this mode until it receives a mode reset (ffh) command. in subsequent frdio execution, the command code is not input, saving timing cycles as described in figure 16. if a frdio i nstruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle figure 1 5 . fast read dual i/o sequence (with command decode cycles) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 8 1 9 2 0 2 1 . . . i n s t r u c t i o n = 1 0 1 1 1 0 1 1 b . . . 2 3 2 2 2 1 2 0 6 4 3 - b y t e a d d r e s s c e # s c k i o 0 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 c e # s c k i o 0 i o 1 d a t a o u t 1 d a t a o u t 2 . . . 2 2 2 0 3 1 7 i o 1 1 9 5 m o d e b i t s 7 6
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 22 device operation (continued ) figure 1 6 . fast read dual i/o sequence (with out command decode cycles) frqo command (fast read quad output) operation the frqo instruction is used to read memory data on four output pins each at up to a 1 0 0 m hz clock. the frqo instruction code is followed by three address bytes (a23 C a0) and a dummy byte (8 clocks), transmitted via the si line, with each bit latched - in during the rising edge of sck. then the first data byte addressed is shifted out on the io3, io2, io1 and io0 lines, with each group of four bits shifted out at a maximum frequency f ct , during the falling edge of sck. the first bit (msb) is output on io3, while simultaneously the second bit is output on io2, the third bit is output on io1, etc. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address , allowing the entire memory to be read with a single frqo instruction. frqo instruction is terminated by driving ce# high (v ih ). if a frqo instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and w ill not have any effects on the current cycle 0 1 2 3 10 11 12 13 14 15 16 17 18 19 20 21 ... ... 23 22 21 2 0 6 4 3 - byte address ce# sck io0 5 4 3 2 1 0 7 6 5 4 data out 1 data out 2 ... 22 20 3 1 7 io1 19 5 mode bits 7 6
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 23 device operation (continued ) figure 1 7 . fast read quad - output sequence 0 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 . . . i n s t r u c t i o n = 0 1 1 0 1 0 1 1 b . . . 2 3 2 2 2 1 3 2 1 0 3 - b y t e a d d r e s s c e # s c k s i s o h i g h i m p e d a n c e 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 5 4 1 0 5 4 1 0 5 4 1 0 5 4 1 0 5 4 c e # s c k i o 0 i o 1 h i g h i m p e d a n c e d a t a o u t 1 d a t a o u t 2 7 6 3 2 7 6 3 2 7 6 3 2 7 6 3 2 7 6 h i g h i m p e d a n c e i o 2 i o 3 d a t a o u t n . . .
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 24 device operation (continued ) frqio command (fast read quad i/o) operation the frqio instruction is s imilar to the frqo instruction, but allows the address bits to be input four bits at a time. this may allow for code to be executed directly from the spi in some applications. the frqio instruction code is followed by three address bytes (a23 C a0) and a mode byte, transmitted via the io3, io2, io0 and io1 lines, with each group of four bits latched - in during the rising edge of sck. the address msb is input on io 3 , the next bit on io 2 , the next bit on io1, the next bit on io0, and continue to shift in alt ernating on the four . the mode byte contains the value ax, where x is a dont care value. after four dummy clocks, t he first data byte addressed is shifted out on the io3, io2, io1 and io0 lines, with each group of four bits shifted out at a maximum fr equency f ct , during the falling edge of sck. the first bit (msb) is output on io3, while simultaneously the second bit is output on io2, the third bit is output on io1, etc. figure 18 illustrates the timing sequence. the first byte addressed can be at a ny memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frqio i nstruction. frqio instruction is terminated by driving ce# high (v ih ). the device expects the next operation will be another frqio. it remains in this mode until it receives a mode reset (ffh) command. in subsequent frdio execution, the command code is not input, saving cycles as described in figure 1 9. if a frqio instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 25 figure 1 8 . fast read quad i/ o sequence (with command decode cycles) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 i n s t r u c t i o n = 1 1 1 0 1 0 1 1 b 2 1 1 7 1 6 4 0 4 3 - b y t e a d d r e s s c e # s c k i o 0 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 1 0 5 4 1 0 5 4 1 0 5 4 1 0 5 4 c e # s c k i o 0 i o 1 d a t a o u t 1 2 0 1 3 5 1 5 i o 1 1 2 m o d e b i t s 5 4 2 2 1 8 1 4 6 2 6 2 3 1 9 1 5 7 3 7 i o 2 i o 3 1 1 1 0 9 8 3 2 7 6 3 2 7 6 3 2 7 6 3 2 7 6 7 6 i o 2 i o 3 d a t a o u t 2 d a t a o u t 3 d a t a o u t 4 4 d u m m y c y c l e s 2 6 2 7
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 26 device operation (continued ) figure 1 9 . fast read quad i/o sequence (without command decode cycles) mr command (mode reset) operation the mode reset c ommand is used to conclude subsequent frdio and frqio operations. it resets the mode bits to a value that is not ax. it should be executed after an frdio or frqio operation, and is recommended also as the first command after a system reset. the timing s equence is different depending whether the mr command is used after an frdio or frqio, as shown in figure 20. figure 20, mode reset command 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 2 1 1 7 1 6 4 0 4 3 - b y t e a d d r e s s c e # s c k i o 0 d a t a o u t 1 2 0 1 3 5 1 5 i o 1 1 2 m o d e b i t s 2 2 1 8 1 4 6 2 6 2 3 1 9 1 5 7 3 7 i o 2 i o 3 1 1 1 0 9 8 d a t a o u t 2 4 d u m m y c l o c k 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 i n s t r u c t i o n = 1 1 1 1 1 1 1 1 b c e # s c k s i o s o h i g h i m p e d a n c e m o d e r e s e t f o r q u a d i / o m o d e r e s e t f o r d u a l i / o i n s t r u c t i o n = 1 1 1 1 1 1 1 1 b
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 27 device operation (continued ) page_prog command (page program) operation the page program (page_prog) instruction allows up to 256 bytes data to be programmed into memory in a single operation. the destination of the memory to be programmed must be outside the protected memory area set by t he block protection ( bp2, bp1, bp0) bits. a pa ge_prog instruction which attempts to program into a page that is write - protected will be ignored. before the execution of page_prog instruction, the write enable latch (wel) must be enabled through a write enable (wren) instruction. the page_prog instru ction code, three address bytes and program data (1 to 256 bytes) are input via the sl line. program operation will start immediately after the ce# is brought high, otherwise the page_prog instruction will not be executed. the internal control logic automa tically handles the programming voltages and timing. during a program operation, all instructions will be ignored except the rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register v ia a rdsr instruction. if the wip bit is 1, the program operation is still in progress. if wip bit is 0, the program operation has completed. if more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the pr eviously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same pag e. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note: a program operation can alter 1s into 0s, but an erase operation is required to change 0s back to 1s. a byte cann ot be reprogrammed without first erasing the whole sector or block. figure 2 1 . page program sequence
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 28 device operation (continued) the quad input page program instruction allows up to 256 bytes data to be programmed into memory in a single operation with four pins (io0, io1, io2 and io3) . the destination of the memory to be programmed must be outside the protected memory area set by the block protection ( bp3, bp2, bp1, bp0) bits. a quad input page program instruction which attempts to program into a page that is write - protected will be ignored. before the execution of quad input page program instruction, the qe bit in the status register must be set to 1 and the write enable latch (wel) must be enabled through a wri te enable (wren) instruction. the quad input page program instruction code, three address bytes and program data (1 to 256 bytes) are input via the four pins (io0, io1, io2 and io3) . program operation will start immediately after the ce# is brought high, otherwise the quad input page program instruction will not be executed. the internal control logic automatically handles the programming voltages and timing. during a program operation, all instructions will be ignored except the rdsr instruction. the pro gress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instruction. if the wip bit is 1, the program operation is still in progress. if wip bit is 0, the program operation has completed. if more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note: a program opera tion can alter 1s into 0s, but an erase operation is required to change 0s back to 1s. a byte cannot be reprogrammed without first erasing the whole sector or block.
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 29 00110010 b 0 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 . . . i n s t r u c t i o n = 0 1 0 1 0 0 1 0 b . . . 2 3 2 2 2 1 3 2 1 0 3 - b y t e a d d r e s s c e # s c k i o 0 i o 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 5 4 1 0 5 4 1 0 5 4 1 0 5 4 1 0 5 4 c e # s c k i o 0 i o 1 d a t a i n 1 d a t a i n 2 7 6 3 2 7 6 3 2 7 6 3 2 7 6 3 2 7 6 i o 2 i o 3 d a t a i n n . . . i o 2 i o 3
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 30 device operation (continued) e rase operation the memory array of the is 25 l q 0 80 is organized into uniform 4 k b yte sectors or 64 k b yte uniform blocks (a block consists of sixteen adjacent sectors). before a byte can be reprogrammed, the sector or block that contains the byte must be er ased (erasing sets bits to 1). in order to erase the devices, there are three erase instructions available: sector erase (sector_er), block erase (block_er) and chip erase (chip_er). a sector erase operation allows any individual sector to be erased with out affecting the data in other sectors. a block erase operation erases any individual block. a chip erase operation erases the whole memory array of a device. a sector erase, block erase or chip erase operation can be executed prior to any programming ope ration. sector_er command (sector erase) operation a sector_er instruction erases a 4 k b yte sector before the execution of a sector_er instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel bit is reset autom atically after the completion of sector an erase operation. a sector_er instruction is entered, after ce# is pulled low to select the device and stays low during the entire instruction sequence the sector_er instruction code, and three address bytes are i nput via si. erase operation will start immediately after ce# is pulled high. the internal control logic automatically handles the erase voltage and timing. refer to figure 2 2 for sector erase sequence. during an erase operation, all instruction will be i gnored except the read status register (rdsr) instruction. the progress or completion of the erase operation can be determined by reading the wip bit in the status register using a rdsr instruction. if the wip bit is 1, the erase operation is still in pr ogress. if the wip bit is 0, the erase operation has been completed. block_er command (block erase) operation a block erase (block_er) instruction erases a 64 k b yte block of the is 25 l q 0 16 . before the execution of a block_er instruction, the write enabl e latch (wel) must be set via a write enable (wren) instruction. the wel is reset automatically after the completion of a block erase operation. the block_er instruction code and three address bytes are input via si. erase operation will start immediately after the ce# is pulled high, otherwise the block_er instruction will not be executed. the internal control logic automatically handles the erase voltage and timing. refer to figure 2 3 for block erase sequence. chip_er command (chip erase) operation a c hip erase (chip_er) instruction erases the entire memory array of a is 25 l q0 16 . before the execution of chip_er instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel is reset automatically after completion of a chip erase operation. the chip_er instruction code is input via the si. erase operation will start immediately after ce# is pulled high, otherwise the chip_er instruction will not be executed. the internal control logic automatically handles the erase vo ltage and timing. refer to figure 2 4 for chip erase sequence.
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 31 device operation (continued) figure 2 2 . sector erase sequence figure 2 3 . block erase sequence figure 2 4 . chip erase sequence
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 32 device operation (continued) program security informati on row instruction (psir) the psir instructions can read and programmed (erase) using three dedicated instructions . the program information raw instruction is used to program at most 256 bytes to the security memory area (by changing bits from 1 to 0, only). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel) bit. the program information row instruction is entered by driving ce# pin low, followed by the instruction code, three address bytes and at least one data byte on serial data input ( si ). ce# pin must be driven high after the eighth bit s of the last data byte has been latched in, otherwise the program information row instruction is not executed. if more than 256 bytes data are sent to a device, the address counter can not roll over . after ce# pin is driven high, the self - timed page program cycle (whose duration is t potp ) is initiated. while the program otp cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed program cycle, and it is 0 when it is completed. at some unspecified time before th e cycle is complete, the write enable latch (wel) bit is reset. n ote: 1 ? n ? 256 figure 30 . program information raw sequence note: 1. the sir address is from 000000h to 0000 ff h. 2. the sir prote ction bit is in the address 000 1 00 h . 0 1 2 3 4 5 6 7 . . . i n s t r u c t i o n = 1 0 1 1 0 0 0 1 b . . . c e # s c k s i 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 . . . . . . c e # s c k s i 8 9 1 0 1 1 2 8 2 9 3 0 3 1 2 4 - b i t a d d r e s s 2 2 2 3 2 1 2 1 0 m s b 7 m s b 6 5 4 3 2 1 0 d a t a b y t e 1 7 6 5 d a t a b y t e 2 d a t a b y t e n 4 1 4 2 4 0 4 3
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 33 device operation (continued) to lock the otp memory: bit 0 of the otp control byte, that is byte 256 , is used to permanently lock the otp memory array. when bit 0 of byte 256 = 1, the 256 bytes of the otp memory array can be programmed. when bit 0 of byte 256 = 0, the 256 bytes of the otp memory array are read - only and cannot be programmed anymore. once a bit of the otp memory has been programmed to 0, it can no longer be set to 1. therefore, as soon as bit 0 of byte 256 (control byte) is set to 0, the 256 bytes of the otp memory array become read - only in a permanent way. any program otp (potp) instruction issued while an erase, program or writ e cycle is in progress is rejected without having any effect on the cycle that is in progress b y t e 1 b y t e 2 b y t e 2 5 6 b y t e 2 5 5 o t p c o n t r o l b y t e b i t 0 x x x x x x x b i t 1 ~ b i t 7 d o n o t c a r e w h e n b i t 0 = 0 t h e 2 5 6 o t p b y t e s b e c o m e r e a d o n l y
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 34 device operation (continued) read security information row (rsir) the rsir instruction read the security infor mation row. there is no rollover mechanism with the read otp (rotp) instruction. this means that the read otp (rotp) instruction must be sent with a maximum of 256 bytes to read, since once the 256 th byte has been read, the same ( 256 th ) byte keeps being re ad on the so pin. fig 3 3 . read security information row instruction 0 1 2 3 4 5 6 7 . . . i n s t r u c t i o n = 0 1 0 0 1 0 1 1 b . . . c e # s c k s i 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 . . . . . . c e # s c k s o 8 9 1 0 1 1 2 8 2 9 3 0 3 1 2 4 - b i t a d d r e s s 2 2 2 3 2 1 2 1 0 m s b 7 m s b 6 5 4 3 2 1 0 d a t a o u t p u r 1 7 6 5 d a t a o u t p u t 2 d a t a o u t p u t n s o 7 0 3 3 3 4 3 6 3 7 3 8 3 9 3 2 3 5 s i 6 5 4 3 2 1 d a t a o u t 0
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 35 device operation (continued) the device allow the interruption of sector - erase, block - erase or page - program o perations and conduct other operations. to enter the suspend/ resume mode: issuing 75 h /b0h for suspend; 7a h /30h for resume suspend to suspend ready timing: 20us. resume to another suspend timing: 1ms. *note: it needs 500ns delay time from write command to suspend command after erase suspend, wel bit will be clear, only read related and resume command can be accepted. (03h, 0bh, bbh, ebh, 05h, abh, 9fh, 90h, 4bh) to execute a program/erase suspend operation, the host drives ce# low, sends the program/erase suspend command cycle ( 75 h /b0h ), then drives ce# high. t he device will not accept another command until it is ready. to determine when the device will accept a new command, poll the wip bit in the status register or wait t ws . program suspend allows the interruption of all program operations. after program suspend, wel bit will be cleared, only read related and resume command can be accepted. ( 03h, 0b h, bbh, ebh, 05h, abh, 9fh, 90h, 4bh) to execute a program/erase suspend operation, the host drives ce# low, sends the program/erase suspend command cycle ( 75 h /b0h ), then drives ce# high. t he device will not accept another command until it is ready. to det ermine when the device will accept a new command, poll the wip bit in the status register or wait t ws . program/erase resume restarts a program/erase command that was suspended . to execute a program/erase resume operation, the host dr ives ce# low, sends the program/erase resume command cycle ( 7a h /30h ), then drives ce# high. to determine if the internal, self - timed write operation completed, poll the wip bit in the status register, or wait the specified time t se , t be or t pp for sector - erase, block - erase, or page - programming, respectively. the total write time before suspend and after resume will not exceed the uninterrupted write times t se , t be or t pp .
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 36 absolute maximum ratings (1) storage temperature - 5 5 o c to +125 o c surface mount lead soldering temperature standard package 240 o c 3 seconds lead - free package 260 o c 3 seconds input voltage with respect to ground on all pins (2) - 0.5 v to v cc + 0.5 v all output voltage with respect to ground - 0.5 v to v cc + 0.5 v v c c (2) - 0.5 v to +6.0 v notes: 1. applied conditions greater than those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. the functional operation of the device conditions that exceed those ind icated in the operational sections of this specification is not implied. exposure to absolute maximum rating condition for extended periods may affect device reliability. 2. maximum dc voltage on input or i/o pins is v cc + 0.5 v. during voltage transitio ns, input or i/o pins may overshoot v cc by + 2.0 v for a period of time not to exceed 20 ns. minimum dc voltage on input or i/o pins is - 0.5 v. during voltage transitions, input or i/o pins may undershoot gnd by - 2.0 v for a period of time not to exceed 2 0 ns. dc and ac operating range part number is 25 l q 0 80 operating temperature (extended grade) - 40 o c to 105 o c operating temperature (industrial grade) - 40 o c to 85 o c operating temperature (automotive, a1 grade) - 40 o c to 85 o c operating temperature ( automotive, a2 grade) - 40 o c to 105 o c operating temperature (automotive, a3 grade) - 40 o c to 125 o c vcc power supply 2. 3 v C 3.6 v dc characteristics applicable over recommended operating range from: v cc = 2. 3 v to 3.6 v (unless otherwise noted). symbol parameter condition min ty p max units i cc1 vcc active read current v cc = 3.6v at 33 mhz, so = open 10 1 2 ma i cc2 vcc program/erase current v cc = 3.6v at 33 mhz, so = open 15 2 0 ma i sb1 vcc standby current cmos v cc = 3.6v, ce# = v cc 10 30 ? a i sb 3 vcc standby current ttl v cc = 3.6v, ce# = v ih to v cc 3 ma i li input leakage current v in = 0v to v cc 1 ? a i lo output leakage current v in = 0v to v cc , t ac = 0 o c to 130 o c 1 ? a v il input low voltage - 0.5 0.3vcc v v ih input high voltag e 0.7v cc v cc + 0.3 v v ol output low voltage 2. 3 v < v cc < 3.6v i ol = 2.1 ma 0.45 v v oh output high voltage i oh = - 100 ? a v cc C 0.2 v
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 37 ac characteristics applicable over recommended operating range from v cc = 2. 3 v to 3.6 v c l = 1 ttl ga te and 30 pf (unless otherwise noted). symbol parameter min typ max units f ct clock frequency for fast read mode 0 1 0 4 mhz f c clock frequency for read mode 0 33 mhz t ri input rise time 8 ns t fi input fall time 8 ns t ckh sck high time 4 ns t ckl sck low time 4 ns t ceh ce# high time 25 ns t cs ce# setup time 10 ns t ch ce# hold time 5 ns t ds data in setup time 2 ns t dh data in hold time 2 ns t hs hold setup time 15 ns t hd hold time 15 ns t v outpu t valid 8 ns t oh output hold time normal mode 0 ns t lz hold to output low z 200 ns t hz hold to output high z 200 ns t dis output disable time 10 0 ns t ec secter erase time 5 0 15 0 ms block erase time (64k b yte) 0. 5 2 s chip erase time ( 8 mb) 2 5 s t pp page program time 0. 5 0. 7 ms t res1 3 ? s ? t dp 3 ? s ? t w write status register time 2 ms ? tws s uspend time 20 us
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 38 ac characteristics (continued) serial input/output timing (1) note: 1. for spi mode 0 (0,0)
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 39 ac characteristics (continued) hold timing pin capacitance (f = 1 mhz , t = 25c ) typ max units conditions c in 4 6 pf v in = 0 v c out 8 12 pf v out = 0 v note: these parameters are characterized but not 100% tested. output test load input test waveforms and measurement level 30pf
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 40 power - up and power - down at powe r - up and power - down, the device must not be selected (ce# must follow the voltage applied on vcc) until vcc reaches the correct value: - vcc(min) at power - up, and then for a further delay of tvce - vss at power - down usually a simple pull - up resistor on ce# can be used to insure safe and proper power - up and power - down. to avoid data corruption and inadvertent write operations during power up, a power on reset (por) circuit is included. the logic inside the device is held reset while vcc is less than the por threshold value (vwi) during power up, the device does not respond to any instruction until a time delay of tpuw has elapsed after the moment that vcc rised above the vwi threshold. however, the correct operation of the device is not guaranteed if, by this time, vcc is still below vcc(min). no write status register, program or erase instructions should be sent until the later of: - tpuw after vcc passed the vwi threshold - tvce after vcc passed the vcc(min) level at power - up, the device is in the following state: - the device is in the standby mode - the write enable latch (wel) bit is reset at power - down, when vcc drops from the operating voltage, to below the vwi, all write operations are disabled and the device does not respond to any write instruction. 2.0 1 50 chip selection not allowed all write commands are rejected tvce read access allowed device fully accessible tpuw vcc vcc(max) vcc(min) reset state v (write inhibit) time symbol parameter min. max. unit t vce *1 vcc(min) to ce# low 10 us t puw *1 power-up time delay to write instruction 1 10 ms v wi *1 write inhibit voltage 2.4 v note : *1. these parameters are characterized only.
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 41 program/erase performance parameter unit typ max remarks sector erase time ms 5 0 15 0 from writing erase command to erase completion block erase time (64kb) m s 500 2 0 00 from writing erase command to erase completion chip erase time ( 8 m b) s 2 5 from writing erase command to erase completion page programming time ms 0.5 0.7 from writing program command to program completion byte program us 10 note: these parameters are characterized and are not 100% tested. reliability character istics parameter min typ unit test method endurance 1 00,000 cycles jedec standard a117 data retention 20 years jedec standard a103 esd C human body model 2,000 volts jedec standard a114 esd C machine model 200 volts jedec standard a115 latch - up 100 + i cc1 ma jedec standard 78 note: these parameters are characterized and are not 100% tested.
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 42 package type information (continued) ` j b 8 - pin jedec 208mil broad small outline integrated circuit (soic) package (measure in millimeters)
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 43 pac kage type information (continued) jp 8 - contact ulta - thin small outline no - lead (wson) package (measure in millimeters)
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 44 package type information (continued) ja 8 - pin 300mil wide body, plastic dual in - line package pdip (measure in millimeters)
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 45 package type information (continued) jv 8 - pin v vsop 150mil
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 46
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 47 appendix1: safe guard function safe guard function is a security function for customer to protect by sector (4k b yte). every sector has one bit register to decide it will under safe guard protect or not. ( 0 means protect and 1 means not protect by safe guard.) is 25 l q0 80 (sector 0~sector 255 ) m apping table for safe guard register address d7 d6 d5 d4 d3 d2 d1 d0 sector0 000h 1 1 1 1 1 1 1 0 sector1 000h 1 1 1 1 1 1 0 1 sector2 000h 1 1 1 1 1 0 1 1 sector3 000h 1 1 1 1 0 1 1 1 sector4 000h 1 1 1 0 1 1 1 1 sector5 000h 1 1 0 1 1 1 1 1 sector6 000h 1 0 1 1 1 1 1 1 sector7 000h 0 1 1 1 1 1 1 1 sector8 001h 1 1 1 1 1 1 1 0 sector9 001h 1 1 1 1 1 1 0 1 sec tor10 001h 1 1 1 1 1 0 1 1 sector11 001h 1 1 1 1 0 1 1 1 sector12 001h 1 1 1 0 1 1 1 1 sector13 001h 1 1 0 1 1 1 1 1 sector14 001h 1 0 1 1 1 1 1 1 sector15 001h 0 1 1 1 1 1 1 1 sector 248 0 1 f h 1 1 1 1 1 1 1 0 sector 249 0 1 f h 1 1 1 1 1 1 0 1 sector 250 0 1 f h 1 1 1 1 1 0 1 1 sector 251 0 1 f h 1 1 1 1 0 1 1 1 sector 252 0 1 f h 1 1 1 0 1 1 1 1 sector 253 0 1 f h 1 1 0 1 1 1 1 1 sector 254 0 1 f h 1 0 1 1 1 1 1 1 sector 255 0 1 f h 0 1 1 1 1 1 1 1 chip e rase disable* 0 2 0 h 0 0 0 0 0 0 0 0 note:1. please set the chip e rase disable to "0" after finished the register setting.
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 48 read safe guard register the read safe guard instruction code is transmitted via the slo line, followed by three address bytes (a23 - a0) of the first regist er location to be read. the first byte data (d7 - d0) addressed is then shifted out on the so line, msb first. the address is automatically incremented after each byte of data is shifted out. the read operation can be terminated at any time by driving ce# high (v ih ) after the data comes out. fig a. timing waveform of read safe guard register erase safe guard register i f we want to erase the safe guard register to let the flash into unprotect status, it needs five continuous instruct ions. i f any instruction is wrong, the erase command will be ignored. erase wait time follow product erase timing spec. fig b. shows the complete steps for erase safe guard register. program safe guard register i f we want to erase the safe guard register to let the flash into unprotect status, it needs five continuous instructions. i f any instruction is wrong, the program command will be ignored. the program safe guard instruction allows up to 256 bytes data to be programmed into memory in a single operat ion. program wait time follow product program timing spec. fig c. shows the complete steps for program safe guard register. 1 st byte 2 nd byte c s s c k s i 1 2 7 8 2 f h 9 1 0 2 3 2 4 a 2 3 - a 0 2 5 2 6 3 1 3 2 d 7 - d 0 d 7 - d 0 3 3 3 4 3 9 4 0 s o 4 1 4 2 4 7 4 8
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 49 fig b. erase safe guard register c s s c k s i 1 2 7 8 9 1 0 3 1 3 2 5 5 h a 2 3 - a 0 s e c t o r p r o t e c t i o n m o d e e r a s e c s s c k s i 1 2 7 8 9 1 0 3 1 3 2 a a h a 2 3 - a 0 c s s c k s i 1 2 7 8 9 1 0 3 1 3 2 8 0 h a 2 3 - a 0 c s s c k s i 1 2 7 8 9 1 0 3 1 3 2 a a h a 2 3 - a 0 c s s c k s i 1 2 7 8 2 b h
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 50 fig c. program safe guard register 1 st byte 2nd byte s c k s i 1 2 7 8 9 1 0 3 1 3 2 2 3 h a 2 3 - a 0 c s d 7 - d 0 d 7 - d 0 3 3 3 4 3 9 4 0 4 1 4 2 4 7 4 8 c s s c k s i 1 2 7 8 9 1 0 3 1 3 2 5 5 h a 2 3 - a 0 c s s c k s i 1 2 7 8 9 1 0 3 1 3 2 a a h a 2 3 - a 0 c s s c k s i 1 2 7 8 9 1 0 3 1 3 2 a 0 h a 2 3 - a 0 c s s c k s i 1 2 7 8 9 1 0 3 1 3 2 5 5 h a 2 3 - a 0
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 51 appendix2: sector unlock function instruction name hex code operation command cycle maximum frequency sect_un lock 26h sector unlock 4 bytes 1 0 0 mhz sect_ lock 24h sector lock 1 byte 1 0 0 mhz sec_un l ock command operation the sector unlock command allows the user to select a specific sector to allow program and erase operations. this instruction is effective when the blocks are designated as write - protected through the bp0, bp1 , bp2 and bp 3 bits in the status register. only one sector can be enabled at any time. to enable a different sector, a previously enabled sector must be disabled by executing a sector lock command. the instruction code is followed by a 24 - bit address specifying the target s ector, but a0 through a11 are not decoded. the remaining sectors within the same block remain in read - only mode. figure d . sector unlock sequence note: 1.if t he clock number will not match 8 clocks(command)+ 24 clocks (address) , it wi ll be ignored. 2.it must be executed write enable (06h) before sector unlock instructions. c s s c k s i 1 2 7 8 9 1 0 1 5 1 6 1 7 1 8 2 3 2 4 2 5 2 6 3 1 3 2 1 2 7 8 0 6 h 2 6 h a 2 3 - a 1 6 a 1 5 - a 8 a 7 - a 0 i n t h e s e c t o r u n l o c k p r o c e d u r e , [ a 1 1 : a 0 ] n e e d s e q u a l t o 0 , u n l o c k p r o c e d u r e i s c o m p l e t e d , o t h e r w i s e c h i p w i l l r e g a r d i t a s i l l e g a l c o m m a n d . s e c t o r u n l o c k
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 52 sect_ l ock command operation the sector lock command reverses the function of the sector unlock command. the instruction code does not requi re an address to be specified, as only one sector can be enabled at a time. the remaining sectors within the same block remain in read - only mode. figure e . sector lock sequence
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 53 product ordering information is 25 lq * ** - j b l e temperature range e = extended grade ( - 40c to +105c) i = industrial grade ( - 40c to +85c) a1 = automotive, a1 grade ( - 40c to +85c) a2 = automotive, a2 grade ( - 40c to +105c) a3 = automotive, a3 grade ( - 40c to +125c) environmental attribute l = lead - free (pb - free) package package type jb = 8 - pin soic 208mil jp = 8 - pin wson ja = 8 - pin pdip 300mil jv = 8 - pin vvsop 150mil device number is25 l q080
is25 l q 080 integrated silicon solution, inc. - www.issi.com rev. a 10 /1 8 /2012 54 ordering information : density frequency (mhz) order part number package 8m 104 IS25LQ080 - jb le 8 - pin soic 208 - mil IS25LQ080 - jp le 8 - pin wson IS25LQ080 - ja le 8 - pin pdip 300 - mil IS25LQ080 - jv le 8 - pin vvsop 150 mil IS25LQ080 - jb l i 8 - pin soic 208 - mil IS25LQ080 - jp l i 8 - pin wson IS25LQ080 - ja l i 8 - pin pdip 300 - mil IS25LQ080 - jv l i 8 - pin vvsop 150 mil IS25LQ080 - jba1 8 - pin soic 208 - mil IS25LQ080 - jpa1 8 - pin wson IS25LQ080 - jaa1 8 - pin pdip 300 - mil IS25LQ080 - jva1 8 - pin vvsop 150 mil IS25LQ080 - jba2 8 - pin soic 208 - mil is25lq0 80 - jpa2 8 - pin wson IS25LQ080 - jaa2 8 - pin pdip 300 - mil IS25LQ080 - jva2 8 - pin vvsop 150 mil

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